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| NJU3711A 8-BIT SERIAL TO PARALLEL CONVERTER GENERAL DESCRIPTION The NJU3711A is an 8-bit serial to parallel converter especially applying to MPU outport expander. It can operate from 2.4V to 5.5V. The effective outport assignment of MPU is available as the connection between NJU3711A and MPU using only 4 lines. The serial data synchronizing with 5MHz or more clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data latches. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. PACKAGE OUTLINE NJU3711AV FEATURES 8-Bit Serial In Parallel Out Hysteresis Input 0.5V typ at 5V Operating Voltage 2.4 to 5.5V Maximum Operating Frequency 5MHz and more Output Current 25mA at 5V, 5mA at 3V C-MOS Technology Package Outline SSOP14 PIN CONFIGURATION P3 P4 P5 VSS P6 P7 P8 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD P2 P1 CLR STB CLK DATA NJU3711AV BLOCK DIAGRAM DATA Shift Register Latch Circuit CLK P1 P2 P3 P7 P8 STB CLR Controller Circuit Ver.2003-11-18 -1- NJU3711A TERMINAL DESCRIPTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL P3 P4 P5 VSS P6 P7 P8 DATA CLK STB CLR P1 P2 VDD I/O O O O O O O I I I I O O FUNCTION Parallel Conversion Data Output Terminals GND Parallel Conversion Data Output Terminals Serial Data Input Terminal Clock Signal Input Terminal Strobe Signal Input Terminal Clear Signal Input Terminal Parallel Conversion Data Output Terminals Power Supply Terminal (2.4 to 5.5V) -2- Ver.2003-11-18 NJU3711A NJU3555 FUNCTIONAL DESCRIPTION (1) Reset When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion output are "L" level. Normally, the CLR terminal should be "H" level. (2) Data Transmission In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal. When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latches. Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore, the clock signal should be controlled for data order. Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure to protect the noise. CLK X STB X H L H L H CLR L H OPERATION All of latches are reset (the data in the shift register is no change). All of parallel conversion outputs are "L". The serial data into the DATA terminal are inputted to the shift register. In this stage, the data in the latch is not changed. The data in the shift register is transferred to the latch. And the data in the latch is output from the parallel conversion output terminals. When the clock signal is inputted into the CLK terminal in state of the STB="L" and CLR="H", the data is shifted in the shift register and latched data is also changed in accordance with the shift register. Note 1) X: Don't care Ver.2003-11-18 -3- NJU3711A TIMING CHART CLK CLR STB DATA P1 P2 P3 P4 P5 P6 P7 P8 -4- Ver.2003-11-18 NJU3711A NJU3555 ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER Supply Voltage Range Input Voltage Range Output Voltage Range Output Current Output Short Current (P1~P8 Terminals) (Note 5) SYMBOL VDD VI VO IO IOSD PD Topr Tstg RATINGS -0.5 ~ +7.0 VSS-0.5 ~ VDD+0.5 VSS-0.5 ~ VDD+0.5 25 VO=7V, VI=0V VO=0V, VI=7V 20 (max) -20 (max) UNIT V V V Ma MA MW C C Power Dissipation Operating Temperature Range Storage Temperature Range 300 (SSOP) -25 ~ +85 -65 ~+150 Note 2) All voltage are relative to VSS=0V reference. Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also Note 4) Note 5) recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. To stabilize the IC operation, place decoupling capacitor between VDD and VSS. VDD=7V, VSS=0V, less than 1 second per pin. DC ELECTRICAL CHARACTERISTICS PARAMETER Operating Voltage Operating Current High-level Input Voltage Low-level Input Voltage Input Leakage Current SYMBOL (VDD=2.4~5.5V, VSS=0V, Ta=25C, unless otherwise noted) CONDITION MIN TYP MAX UNIT 2.4 VIH=VDD, VIL=VSS 0.7VDD VSS VI=0~VDD IOH=-25mA VDD IDDS VIH VIL ILI - 5.5 0.1 VDD 0.3VDD 10 VDD VDD VDD VDD 1.5 0.8 0.4 0.5 V mA V V A -10 VDD-1.5 P1~P8 Terminals High-level Output Voltage (Note 6) VOHD VDD=5V IOH=-15mA IOH=-10mA VDD-1.0 VDD-0.5 VDD-0.5 VSS V VDD=3V IOH=-5mA IOL=+25mA Low-level Output Voltage (Note 6) VOLD VDD=5V IOL=+15mA IOL=+10mA P1~P8 Terminals VSS VSS VSS V VDD=3V operation should be required. IOL=+5mA Note 6) Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating Ver.2003-11-18 -5- NJU3711A SWITCHING CHARACTERISTICS PARAMETER Set-Up Time Hold Time Set-Up Time Hold Time SYMBOL tSD tHD tSSTB tHSTB tpd PCK Output Delay Time tpd PSTB tpd PCLR Maximum Operating Frequency (VDD=2.4~5.5V, VSS=0V, Ta=25C, unless otherwise noted) CONDITION MIN TYP MAX UNIT DATA-CLK CLK-DATA STB-CLK CLK-STB CLK-P1~P8 STB-P1~P8 CLR-P1~P8 20 20 30 30 5 100 80 80 ns ns ns ns ns ns ns MHz fMAX Note 7) COUT=50pF -6- Ver.2003-11-18 NJU3711A NJU3555 SWITCHING CHARACTERISTICS TEST WAVEFORM fMAX CLK tSD DATA tHD STB tHSTB tSSTB CLK tpd PCK L STB P1~P8 CLK H STB tpd PSTB P1~P8 CLR DATA tpd PCLR H P1~P8 Ver.2003-11-18 -7- NJU3711A APPLICATION CIRCUIT MPU DATA CLK STB CLR P1 P2 P3 P4 P5 P6 P7 P8 NJU3711A [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -8- Ver.2003-11-18 |
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